1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same. In particular, it relates to a semiconductor device including a DRAM cell composed of a trench capacitor and a cell transistor, and a method of manufacturing the same.
2. Description of the Related Art
A DRAM including 1-transistor/1-capacitor memory cells is required to have a downsized cell area for high integration. Downsizing of the cell area basically requires reductions in respective areas occupied by components, or the transistor and the capacitor. As for the capacitor, the problem is how to ensure a required capacitor capacitance in a small cell-occupied area. Thus, developments are proceeding in structure and so forth for achieving a high-permittivity capacitor insulator and for increasing an effective capacitor area. Another DRAM is also widely employed, which includes a capacitor having a trench capacitor structure extending in a direction perpendicular to a substrate. In such the trench capacitor structure, it is important to structure a connection between a storage node electrode of the trench capacitor and a source/drain-diffused layer of a cell transistor.
A buried strap structure is known as one of those structures. The buried strap is formed by burying material such as polysilicon in the trench to connect the storage node electrode of the trench capacitor to the source/drain-diffused layer of the cell transistor. A method of manufacturing a semiconductor device including such the buried strap is known from JP-A 2001-196555 (paragraphs [0044]-[0045], Patent Document 1), for example. In the manufacturing method of Patent Document 1, a buried strap is formed adjoining transistor formation regions at both left and right sides on the trench capacitor. Then, an island-shaped resist pattern for formation of device isolation trenches (STI) is formed per a number of trench capacitors formed in the shape of a grid. Thereafter, the island-shaped resist pattern is used as a mask for etching one side of the buried strap. Then, a device isolation film is buried in device isolation trenches formed by the etching to form a buried strap that connects one cell transistor to one trench capacitor. It becomes difficult to form such the island-shaped resist pattern as shown in Patent Document 1, however, as fine patterning of elements proceeds.
To solve the problem, there is a method of manufacturing a semiconductor device including a buried strap, which is manufacturable without forming the discrete island-shaped resist pattern and only with the so-called line-and-space shaped resist pattern. This method is proposed by J. Amon et al., A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70 nm technology, IEDM Tech. Dig, pg. 73, 2004 (Non-Patent Document 1). In the manufacturing method of this document, a buried strap is formed adjoining transistor formation regions at both left and right sides on the trench capacitor. Then, a silicon nitride film and an amorphous silicon film are deposited over the entire surface including the inside of the trench for a trench capacitor. Thereafter, ions of boron (B) or the like are implanted into the amorphous silicon film by slanting ion implantation to introduce B into the amorphous silicon film except for the portion shaded on ion implantation. Then, an alkali-based wet etching is applied to etch the amorphous silicon film off the portion to which B is not introduced, and followed by wet etching to etch the silicon nitride film off the portion from which the amorphous silicon film was removed. Thereafter, the remaining amorphous silicon film and the buried strap are removed with a mask of the silicon nitride film. A device isolation film is buried in the device isolation trench thus formed to form a buried contact that is brought into contact with only one side of the transistor formation region. The manufacturing method of this non-patent document requires no formation of the island-like separated resist pattern and can respond to proceeding of fine patterning. There is a problem in the method, however, because formation of the amorphous silicon film that does not eventually become a component of the device increases the number of process steps and increases the production cost correspondingly.